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Honored Contributor

12 years ago

Help: how to write a 20ns delay on verilog HDL

how to write a 20ns delay on verilog HDL? simple example pls thanks

Honored Contributor

12 years ago

Synthesizable:

always @ (posedge clk)
data_delayed <= data;

(clk is 50 MHz)

Non-synthesizable:

`timescale 1ns / 1ps
<module declaration stuff>
always @*
data_delayed =# 20 data;