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Altera_Forum
Honored Contributor
13 years agoAs FvM wrote, you try to process one pixel per clock and the RAM access sequence can get very complicated depending on the amount of data you need to reference to produce an output pixel. As part of the Video and Image Processing Suite of IP, Altera supplies a 2-D FIR Filter which may be useful to you. You may find the book "Design for Embedded Image Processing on FPGAs" by Donald G Bailey useful. Chapter 8 Local Filters covers this particular topic pretty well.