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Altera_Forum
Honored Contributor
13 years agoC image processing can't be simply copied to VHDL, it has to be basically redesigned. Available FPGA resources suggest a sequential processing of image data stored in FPGA internal or more likely external RAM. Sequential processing involves state machines and sequence controllers, not for loops. HDL iteration schemes are describing parallel processing and tend to make FPGA resource utilization "explode" for large data structures.