Contributorafter few days struggle, I figured out that when edit the ip, set the simulation file as copy from the synthesize. then regenerate the ip testbench. it will solve this problem.
thanks,
David
ContributorQuestion Related to the same issue.
I try to regenerate the IPs. here are the Error message for some modules.
Error: reg_ctrl_0: reg_ctrl does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Error: SPD file was not generated: C:\FPGA\TSW14J57_pro\copy3\ip\ip\jesd204b\jesd204b_reg_ctrl_0\jesd204b_reg_ctrl_0.spd
Error: Could not generate simulation scripts
in this situation, if a module .spd file couldn't be generated, then the Generate simulation setup script can't execute successfully. how can I create a simulation environment for the project?
is there a command that can exclude the modules that not supported for the spd file generation? then added to the whole project manually.
thanks,
David
Contributorafter few days struggle, I figured out that when edit the ip, set the simulation file as copy from the synthesize. then regenerate the ip testbench. it will solve this problem.
thanks,
David
