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Honored Contributor
Honored ContributorHELP - Hardware register
Hello :)
I have created a register, but I am not able to make it work with every clock cycle. It works good with the reset, but with the clock it automatically enters to the "others" option Any hints?library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity registro_desp is
PORT (entradax: in std_logic_vector (7 downto 0);
salida: out std_logic_vector (14 downto 0);
contador : in std_logic_vector (3 downto 0);
clk: in std_logic;
reset: in std_logic
);
end registro_desp;
architecture Behavioral of registro_desp is
signal Q: std_logic_vector(14 downto 0);
begin
reg_desp: process (clk, reset)
begin
if (reset ='0' and clk = '1' and clk'event) then
CASE contador is
when "0001" => Q <= ('0' & entradax & "000000");
when "0010" => Q <= ('0' & entradax & "000000");
when "0011" => Q <= ("00" & entradax & "00000");
when "0100" => Q <= ("00" & entradax & "00000");
when "0101" => Q <= ("000" & entradax & "0000");
when "0110" => Q <= ("000" & entradax & "0000");
when "0111" => Q <= ("0000" & entradax & "000");
when "1000" => Q <= ("0000" & entradax & "000");
when "1001" => Q <= ("00000" & entradax & "00");
when "1010" => Q <= ("00000" & entradax & "00");
when "1011" => Q <= ("000000" & entradax & "0");
when "1100" => Q <= ("000000" & entradax & "0");
when "1101" => Q <= ("0000000" & entradax);
when "1110" => Q <= ("0000000" & entradax);
when others => Q <= (entradax & "0000000");
--wait until CLK'EVENT and CLK = '1'; --I THOUGHT THAT THIS WOULD WORK, BUT IT DIDN'T :(
END CASE;
elsif reset='1' then Q<="000000000000000";
salida<=Q;
end if;
end process;
end Behavioral;
