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Altera_Forum
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8 years ago

Help - Creating alarm clock with modulo counter - System verilog

I am trying to create an alarm clock using a Terasic CycloneV fpga. I need to be able to set the time and an alarm. Right now I'm unable to get the clock to reset at 24 hours. I have attached the mod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The reason for the always_ff block not working is because you'v used the bit-wise AND (&) operator and not the logical AND (&&). Change the '&' to '&&' and try. It will trigger this time. 


/*this is the part that doesn't work        
always_ff @(posedge oneSecondEnable) begin
    if (rollHourTens ==2 & rollHourOnes==4) begin  <------ Change this to logical && from the bitwise &
        reset;
    end
end
*/