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ACoga
New Contributor
New ContributorHello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.
Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen sim...
ACogaNew Contributor
New ContributorThank you @sstrell , I'm updating the .sdc file.
I checked the paths with the Technology Map and the failures really caused by feedback loops. But these loops are in different Altera's IPs code - FIFO, EPCS controller so it is not clear what they are doing exactly...
I'll try to understand better what happens.
Thank you for your help.
