Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

Thank you @sstrell​ , I'm updating the .sdc file.

I checked the paths with the Technology Map and the failures really caused by feedback loops. But these loops are in different Altera's IPs code - FIFO, EPCS controller so it is not clear what they are doing exactly...

I'll try to understand better what happens.

Thank you for your help.