Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

A few things: 1) for a hold analysis, you should be looking at the fast timing model. 2) Your report_timing command is looking at all paths latched by clk[0]. Is this what you intend to look at? I would want to see you scroll down in that data path tab to try to figure out why the from and to nodes are the same. I would also want to see your .sdc, and your clock and clock summary reports. It's hard to diagnose with what you have here.