New ContributorHello, I am trying to complete this task but having issues with compiling. Fingers crossed the code it works on my DE10-Lite board.
module DE10_LITE_Default(a,b); // circuitA
input [2:0]a;
output [2:0]b;
assign b[2:0] = (a[2:0] == 3'b010) ?3'b000 : // 2 ? 0
(a[2:0] == 3'b011) ?3'b001 : // 3 ? 1
(a[2:0] == 3'b100) ?3'b010 : // 4 ? 2
(a[2:0] == 3'b101) ?3'b011 : // 5 ? 3
(a[2:0] == 3'b110) ?3'b100 : // 6 ? 4
(a[2:0] == 3'b111) ?3'b101 :3'b111; // 7 ? 5 : 7
endmodule
//--------------------------------------
module DE10_LITE_Default_B(a,hex); // circuitB
input [0:0]a;
output [6:0]hex;
assign hex[6:0] = (a[0] == 1'b1)? 7'b111_1001 : 7'b100_0000; // 1 - 0
endmodule
//-----------------------------------------
module multi(s,x,y,m);
input s;
input [3:0]x,y;
output [3:0]m;
assign m[3] = (~s&x[3] ) | (s&y[3]);
assign m[2] = (~s&x[2] ) | (s&y[2]);
assign m[1] = (~s&x[1] ) | (s&y[1]);
assign m[0] = (~s&x[0] ) | (s&y[0]);
endmodule
//------------------------------------------
module char_7segs(sw,hex);
input [3:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[3:0] == 4'b0000 )? 7'b100_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: // 1
(sw[3:0] == 4'b0010 )? 7'b010_0100: // 2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b000_0111: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_1000:7'b111_1111; // 9 - blank
assign hex= (sw[7:4] == 4'b0000 )? 7'b100_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: // 1
(sw[3:0] == 4'b0010 )? 7'b010_0100: // 2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b000_0111: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_1000:7'b111_1111; // 9 - blank
endmodule
module BCDADD1(A1,A0,B1,B0,S0,S1,S2);
input [3:0] A1, A0, B1, B0; //4 bit inputs
output reg [3:0] S0,S1; // 4bit sum why not wire typ?
output reg S2;// 1 bit carry-out
wire S1carry;
always @(*)
begin
//LSB addition
{S1carry,S0}=A0+B0; // 4-bit add 4-bit to produce 4 bit result and 1 bit carry out
if (A0+B0>9) // otherwise, no correction, S1=0, S0=A0+B0
begin
S0=A0+B0-10;// or S0=A0+B0+6// to have ‘ones’ in S0 as 3 in 13
S1carry=1;// carry-out
//LSB+1 addition
{S2,S1}=A1+B1+S1carry; // 4-bit add 4-bit to produce 4 bit result and 1 bit carry out
if (A1+B1+S1carry>9) // otherwise, no correction, S1=0, S0=A0+B0
begin
S1=A1+B1+S1carry-10;// or S0=A0+B0+6// to have ‘ones’ in S0 as 3 in 13
S2=1;// carry-out
end
end
end
endmodule
Error (10137): Verilog HDL Procedural Assignment error at DE10_LITE_Default.v(263): object "S1carry" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at DE10_LITE_Default.v(267): object "S1carry" on left-hand side of assignment must have a variable data type
