header file in verilog / a better way to define global constants

Keep in mind that if your header file is just a collection of constants it is not a compile-able unit. For example, if defines.v is:

localparam FOO = 6;
localparam BAR = "BAR";

This code needs to be scoped inside a module. So, if you are passing defines.v in a list of files to your compiler, that is your problem. Instead, you'll need to add the path to defines.v in your Verilog include path.

As an aside, I (and at least a few other people I've seen online) use .vh as the file extension for Verilog files which will be `included. This allows you to see which files define modules and which files define constants, functions, etc. Also, some tools will search a given path for files to compile based on module instantiation. This convention prevents such modes of operation from stumbling on code which can't be compiled on its own.