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Altera_Forum
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10 years ago

HDMI IP Core generation mode settings using Quartus 15.1

I have generated HDMI IP core using Quartus version 15.1. I have generated sink IP (Receiver) and connected our source VIP with that. The output mode signal was "0" which means DVI is set, How ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hello manishchand, did you get the core to work at the end?

I am currently having problems reading SCDC offset 0x40, only clock is locked but not the 3 data channels, any similar experience?

Thanks in advance!