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Altera_Forum
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10 years ago

HDMI IP Core generation mode settings using Quartus 15.1

I have generated HDMI IP core using Quartus version 15.1. I have generated sink IP (Receiver) and connected our source VIP with that. The output mode signal was "0" which means DVI is set, How ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The EDID information is typically read from the display over an I2C link. It is implemented as an I2C memory device. Search for VESA EDID on the internet to find documentation of the data provided in the I2C memory device.