HDL Testbench in ModelSim Altera Edition

Thanks for the above feedback and the sample project, everyone has been quite helpful here.

After some more work I've gotten the testbench and FPGA implementation that run through Xilinx ISE to run with the same results in Modelsim AE, with some modifications (substitutions of Xilinx specific IDDR2 blocks and some differences between what environments allow).

As you mentioned above I'm used to Xilinx's tools, the simulation integration in ISE really streamlines the whole process but allows the user to pretty much ignore the inner workings of ModelSim. I think I'll be spending some time reviewing the ModelSim user guide.