Having trouble simulating the dcfifo Megafunction

Sounds reasonable, since the issue clearly stems from the tool not being able to resolve the dcfifo module.

Since I'm primarily working on a system that has VCS installed, and not any Altera collateral, I tried dumping the /verilog/altera_mf/dcfifo file into an area, and including the files with a command line option when calling VCS. I'm not having any luck so far, but have ran out of time to play with it. I'll have to wait until next Tuesday to spend more time on it.

Thanks again for the help, I'll provide some feedback when I get a chance.