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Altera_Forum's avatar
Altera_Forum
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11 years ago

Having trouble simulating the dcfifo Megafunction

I'm quite sure this information must exist somewhere, but I have searched for quite a while now, cannot seem to find it, and am becoming frustrated. background: I am working on a system verilog...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I posted some Altera FIFO examples a while back, give those a try ...

http://www.alteraforum.com/forum/showthread.php?t=38988

At least this should get you a working Modelsim build.

The example is in VHDL, but a verilog design would be similar. If you still cannot get something working, post a simple verilog testbench and I'll get it to work.

Cheers,

Dave