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Altera_Forum
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10 years ago

Hard DDR3 Controller Fitting Problem on Cyclone V

Hi I have generated the DDR3 controller IP from IP Catalogue, using Quartus Prime v15.1; It generated an example design project too. After I assign my DDR3 pins to the FPGA pins & run the "..._p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

According to Altera Cyclone V pin-out file, the HMC pins are fixed and the address_bus[13] MUST be tied to C8 (for my device part number), so this is the problem & should be corrected.

Thanks gj_leeson.