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Altera_Forum
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9 years ago

Hard DDR3 Controller Fitting Problem on Cyclone V

Hi I have generated the DDR3 controller IP from IP Catalogue, using Quartus Prime v15.1; It generated an example design project too. After I assign my DDR3 pins to the FPGA pins & run the "..._p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I'm (now) using a 5CEFA5F23. I found the problem in a very circuitous way, but finally let the compiler choose the device and the pinout and it compiled successfully. This led me to look at the package options and finally the document that described the various limitations. Your problem sounds different and unfortunately I can't shed any light. I learned long ago, however, to make sure the compiler is happy with the device selection and pinout before committing to a PCB.