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Altera_Forum
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10 years ago

Hard DDR3 Controller Fitting Problem on Cyclone V

Hi I have generated the DDR3 controller IP from IP Catalogue, using Quartus Prime v15.1; It generated an example design project too. After I assign my DDR3 pins to the FPGA pins & run the "..._p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I looked at "External Memory Interface Handbook" and in Table 6-5 it has been noted that A4 with F484 package supports X16 mode on the top side (my case); So this should not be my problem.

BUT:

When I changed the mem_a[13] (the failing node in the Fitter report) to pin C8 instead of G6 the Fitter succeeds. My problem is resolved this way, but WHY????

It is difficult to change PCB, so it would be beneficial if I could figure out the problem and resolve it inside the FPGA.

Thanks