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You need to add a SystemID block to your Qsys design. This block is used by eclipse to verify that it is connecting to the correct Nios processor (some designs have more than one).
You can find this peripheral under "Basic Functions -> Simulation; Debug and Verification -> Debug and Performance -> System ID Peripheral".
Connect this up to your Nios processor data master, and set the 32-bit system ID parameter to a hexadecimal value of your choosing.
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More critically, you are also You are also missing the connection between the "debug_reset_request" signal, and the "reset" signal on the Nios processor. This connection is required in order to allow the JTAG debugger to be able to reset the Nios processor and connect to it.
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As a final point, make sure your clock and reset are connected to FPGA pins in your project (outside Qsys) and that both pins are running correctly (reset is correct polarity, and clock is ticking).
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Thanks, I got an error in the synthesis&analysis, The error says that I already have a a module in this name (because of the new "system ID"):
"Error (10228): Verilog HDL error at neek10_qsys_sysid_qsys_0.v(34): module "NEEK10_QSYS_sysid_qsys_0" cannot be declared more than once"
this pin:"debug_reset_request" is inside the :"Nios processor" (which named "cpu"), so I have difficult time to understand what do you mean.
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