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Altera_Forum
Honored Contributor
11 years agoGuidance on SPI Interface Stratix III with ADC DAC Loopback in Verilog
I have basic Verilog fundamentals from undergrad with Xilinx and the Nexys2 Spartan-3E board. I'm currently new into Altera Quartus II software (did the tutorials) and working with the Stratix III E...
Altera_Forum
Honored Contributor
11 years agoA quick search for "verilog spi module" returns plenty of links that should help. If you have some basic verilog understanding you should be able to fathom some of what's there. You might want to start by looking through this example (https://github.com/zouppen/simulavr/blob/master/examples/verilog/spi.v). Equally useful is this link (http://www.elecdude.com/2013/10/spi-verilog-code-master-slave-code-with.html). Note: these are both somewhat idealistic implementations and wouldn't be how I would implement an SPI interface for a real application. However, they should prove very useful exercises.
As for verification - you don't list simulation. Essential, long before you get to SignalTap or an oscilloscope. The link above has a suitable test harness included. Cheers, Alex