Got problems on running 32*32 multiplier vhdl code running on quartus at linux OS

32*32 vhdl code is

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

use work.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mult32bit is

generic (

DATA_WIDTH : integer := 32

);

port(

a : in std_logic_vector(DATA_WIDTH-1 downto 0);

e : in std_logic_vector(15 downto 0);

--PARAM

d : in std_logic_vector(15 downto 0);

--PARAM

c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0)

);

end mult32bit;

architecture Behavioral of mult32bit is

signal b : std_logic_vector(31 downto 0);

signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);

signal left : std_logic_vector((DATA_WIDTH)-1 downto 0);

signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0);

signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0);

begin

b <= e & d;

MULTIPLIER_right:entity work.mult16bit

port map(

a => a(15 downto 0),

b => b(15 downto 0),

c => right

);

MULTIPLIER_left:entity work.mult16bit

port map(

a => a(31 downto 16),

b => b(31 downto 16),

c => left

);

left_shifted <= left & "00000000000000000000000000000000" ;

-- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));

new_right <= "00000000000000000000000000000000" & right;

c <= unsigned(new_right) + unsigned(left_shifted) ;

end Behavioral;

mult16bit code is

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

use work.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mult16bit is

generic (

DATA_WIDTH : integer := 16

);

port(

a : in std_logic_vector(DATA_WIDTH-1 downto 0);

e : in std_logic_vector(7 downto 0);

--PARAM

d : in std_logic_vector(7 downto 0);

--PARAM

c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0)

);

end mult16bit;

architecture Behavioral of mult16bit is

signal b : std_logic_vector(15 downto 0);

signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);

signal left : std_logic_vector((DATA_WIDTH)-1 downto 0);

signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0);

signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0);

begin

b <= d & e;

MULTIPLIER_right:entity work.mult8bit

port map(

a => a(7 downto 0),

b => b(7 downto 0),

c => right

);

MULTIPLIER_left:entity work.mult8bit

port map(

a => a(15 downto 8),

b => b(15 downto 8),

c => left

);

left_shifted <= left & "0000000000000000" ;

-- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));

new_right <= "0000000000000000" & right;

c <= unsigned(new_right) + unsigned(left_shifted) ;

end Behavioral;

my errors are

Error (10349): VHDL Association List error at mult32bit.vhd(42): formal "b" does not exist mult32bit.vhd Line: 42

Error (10346): VHDL error at mult32bit.vhd(38): formal port or parameter "e" must have actual or default value mult32bit.vhd Line: 38

Error (10784): HDL error at mult16bit.vhd(21): see declaration for object "e" mult16bit.vhd Line: 21

Error (10346): VHDL error at mult32bit.vhd(38): formal port or parameter "d" must have actual or default value mult32bit.vhd Line: 38

Error (10784): HDL error at mult16bit.vhd(23): see declaration for object "d" mult16bit.vhd Line: 23