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Altera_Forum's avatar
Altera_Forum
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11 years ago

Good/bad practice wires vs registers.

I was wondering from what perspective it makes sense to do one or the other..

For convenience it would make sense to have overhead variables stored for different global settings, that would be stored in a register and have wires going to various macros in need of the value. Afaik this would be low on memory blocks and convenient.

But how does this relate to overall build quality?

And does having the values stored close to the source multiple times have advantages over the other?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    If you mean the case when same constants are needed by various modules then it is better practice to reduce routing by wiring the same constant to all modules rather than declare constants per module. For example you may have 5 modules each using same 40 coeffs (15 bits each) this means 40 * 15 = 600 wires connected to gnd/source per set.

    If each module declares same constants you get 600 x 5 = 3000 wires.

    Assuming the compiler did not realise that.

    You should not waste registers for constants (through using reset and clked process) as may end up using 3000 registers instead of 600 wires.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    You should not waste registers for constants (through using reset and clked process) as may end up using 3000 registers instead of 600 wires.

    --- Quote End ---

    Thanks, that's exactly it. They're big variables too, lots of wires to go around. :)

    Does this mean to use parameters wherever it can be done?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Synthesis will tie off constants and reduce logic appropriately. You really don't have to worry about it. Parameters are technically better because they occur in the beginning of synthesis, whereas wires create logic which then gets reduced, and therefore is a little slower. But we're really quibbling over little things. I bet you could do it either way and never notice the difference.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks,

    once again the synthesizer prooves to be very well versed. :cool:
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Thanks,

    once again the synthesizer prooves to be very well versed. :cool:

    --- Quote End ---

    Ehm, that finale sounds a bit too optimistic to me. The general rule of thumb is to try writing Verilog as similar as possible to commonplace style, or you may wake up a hidden bug of the synthesizer. So even though the parameters vs. wires discussion should in theory end with "it doesn't matter", and odds are that it really doesn't matter (because the synthesizer should end up with the same result), I would try to look on Altera's sample code and Verilog that it generated in conjunction with IP cores etc. And get the spirit from there.

    Just to play it safe.

    Cheers,

    Andrew.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Just define parameters in the top-most level in which they are used, and then pass those parameters to all the sub-modules that use them, this way you only need to change the parameters once in the top-most module, and all values will be consistent.

    Regarding optimizations the compiler will do that for you, but to do it well it needs to establish as soon as possible that the parameters are constant. The earlier it establishes that in the compiler processes the better. Therefore using Verilog "parameters" is the defacto standard way to do it.

    Regards,

    Amilcar
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Ehm, that finale sounds a bit too optimistic to me. The general rule of thumb is to try writing Verilog as similar as possible to commonplace style, or you may wake up a hidden bug of the synthesizer. .

    --- Quote End ---

    --- Quote Start ---

    Regarding optimizations the compiler will do that for you, but to do it well it needs to establish as soon as possible that the parameters are constant. The earlier it establishes that in the compiler processes the better. Therefore using Verilog "parameters" is the defacto standard way to do it.

    --- Quote End ---

    Alright yes,

    It makes some sense also to do it like that, so you can have a config file with all your divisions and settings. "And litlle formulas and scribble"