Global/Regional Clock Assignment

Thanks for the informative reply!!

The large-fanout clock comes from an output (regular I/O) pin.

For all of the failing paths, the source and the destination clocks are different clocks. Actually, the large-fanout clock is on the launch path of all setup time violations, and it is also on the latch path of hold time violations. That's why I am thinking if I can cut into the delay time on that large-fanout clock, I might be able to solve all timing problems. Currently, delay from the large fan-out clock driving a register is about 4ns, whereas the clock period is only 8ns (it is a PCIe clock signal, so the clock period is fixed and cannot be slowed). The worst setup time slack is about -1.2ns and the worst hold-time slack is -0.4ns.

In terms of clock skew, I cant recall the exact numbers, but I dont think there is a big difference between the skew on the launch and and the skew on receiving paths.

So, it seems that moving the clock signal to regional clock line wont help me much. Does that mean I should try modifying the RTL design (which might be a lot of work). Or, are there anything else easy and obvious in Quartus that I can do to solve the timing issues. I have tried a lot of setting already like increasing the routing effort, optimize speed during synthesis, etc (basically most of the suggestions in the timing optimization advisor).