Global/Regional Clock Assignment

Is it coming from a PLL? PLL outputs always drive globals(which includes regionals) so Auto Global Clock has no affect, and I would be surprised if they obeyed max fanout constraints, since one of the benefits of globals and regionals is that you don't care about fanout. You said there were setup and hold failures, but I don't think moving it from a global to a regional will help either, at least on any path where this clock feeds both the source and destination registers. For setup and hold, the only part of the clocck tree that comes into play is the clock skew, and globals and regionals both have extremely low clock skews. In fact, both are guaranteed not to have hold violations. The main reason to use regionals(besides the fact that there are more of them), is that the actual delay to the registers is shorter, so they can get faster Tcos or things like that. So in your case moving to a regional will probably not help(it might take a few ps of the setup, but that's it), and splitting the fan-out onto multiple globals would only hurt.