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Honored Contributor
Honored ContributorGlobal memory access 512 bit width constrain?
Hi I'm building 2d fft for image processing from the design example provided by Altera, namely modify it to take advantage of Hermitian symmetric: use N/2 point fft to perform a N point real...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Remember that with the kernel running at the same operating frequency as the memory controller (266 MHz in case of 2133 MHz memory) the FPGA external memory bandwidth will be saturated with two 512-bit accesses (read or write) per clock. --- Quote End --- Thank you for the information, I'm not aware of this. Why would kernel running at 266MHz with 2133MHz memory saturate at 1024bits access? Any documentation? Thanks.
