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Altera_Forum
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11 years ago

global clock delay

hi All i have 8 rgmii interfaces, 125M ddr source synchronous. each input has 1clk, 1datavalid and 4data signals. i implement it using ddio. constraint it like this: set_input_delay -...
Altera_Forum's avatar
Altera_Forum
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11 years ago

the difference between setup and hold is caused by DQ pin.

Cyclone V DQ pin used for user pin(not DDR DQ pin), always need to route through HMCPHY_RE. this routing element would cause almost 2ns differnece between setup and hold. no way to bypass it.

so never use DQ pins as high speed input or output in cyclone V