I will have to request authorisation for that, supplying anything else but the source is ok.
But in the meantime let me furnish you with as much detail as possible.
- Using, Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition.
- Its a design which has several VHDL libraries (no work library), let's call them A, B and C
- Most of the files are compiled into library B, top in in library A and a small set of files are in library C
- 3 files are compiled both in library B and library C
- Packages (let's call P) of the same name and records (let's call R) are compiled into library B and library C. Each library's record R is different, in terms of members, sizes etc.
- The 3 files use this package/record and so implement different things although they share files and package/record names
- In top ... each package/record/entity is referred to by its library prefix, for example ... B.entityWithSameName or C.entityWithSameName .... signal w_b : B.recordWithSameName; ... etc.
- Compiling through the GUI works fine (only when I build all, but this is acceptable as I have some pre flow scripts etc.)
- Compiling through command line (quartus_sh) only works the first time - we have a modified version of a quartus.tcl script which executes the flow ... I will minimise it and include that here. Presumably something is missing from this TCL script (?), executed using quartus_sh -t <tcl>.
# Copyright (C) 1991-2013 Altera Corporation
...
# project is open here
set MAX_ATTEMPTS [expr [lindex $argv 1]]
source quartus.qsf
export_assignments
set attempt 0
while {$attempt < $MAX_ATTEMPTS} {
set attempt [expr {$attempt + 1}]
execute_flow -compile
if { ...no violations in timing ...} {
puts "Timing OK. No violation found."
break
} else {
if {..maximum attempts...} {
break
} else {
# rerun ... delete firmware RBF file
# removing assignments to ensure library mapping can be reset
# remove_all_global_assignments -name VHDL_FILE
}
}
}
- I have really minimised the above, kindly excuse if something obvious is missing (just to be clear I didn't write it, so it could have mistakes!).
- How does the problem exhibit itself. From the messages generated I can not see any difference from two consecutive runs except when the problem happens. I will try to explain best I can. On the second run, during analysis and synthesis, when the compiler hits the entity in library B inside top (B.entityWithTheSameName) ... it picks up the package from the other file. I know this because there is a warning for unused variable in the package and instead of saying Warning at fileBWithSameNamePackage,vhd, it says Warning at fileAWithSameNamePackage.vhd - almost as if it had lost the library namespace somehow and picked up the first file with the package in it. A record in the package is input into the entity, so the errors complain about "Error (12002): Port "..." does not exist in macrofunction". And so on the error compounds onto other things.
A few other points:
- At the end of first run, I can see the library mappings are correct by looking at the map.rpt file, all files are correctly placed in A and B.
- Obviously second run does not finish and I cannot verify how this has gone wrong.
- I attempted to reassign library mappings, so I executed remove_all_global_assignments -name VHDL_FILE between runs, that fixed the second run but the third failed (again I wasn't exactly sure what I was doing there).
- If there was a way to (correctly) query whether the global assignment for the files to libraries is correct, that would help is knowing that the problem has happened. And to correct it, how to overwrite these assignments by the correct ones.
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