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Altera_Forum's avatar
Altera_Forum
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16 years ago

Getting the simulation time in a testbench

Hi there, does anyone know how to get the simulation time in a VHDL testbench? Is there a better method than just adding how much time was "wait"ed? Thanks for any reply, Kjellski
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thank you very much,

that´s what I was looking

for.

Greetings,

Kjellski