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New Contributor

7 years ago

Getting platform designer to find `include files

How do you get platform designer to generate the proper tcl files so that when a verilog file has an include statement the file is found for both synthesis and simulation? This question has been as...

KennyT_altera

Super Contributor

7 years ago

In the platform designer, you can add those file

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf

page 566

Set to the correct output_files where you want to store it. Then the path of this include have to be same for your output_files so that quartus able to synthesis it.

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Getting platform designer to find `include files

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