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bteddy's avatar
bteddy
Icon for New Contributor rankNew Contributor
3 years ago

Getting errors when I run analysis and elaboration.

Hello, I have a verilog file "10ustep_stepperdriver.v" attached. Using Quartus II 64-bit ver.13.1 web edition. I was trying to run analysis and elaboration to get a RTL netlist (schematic). I...
hareesh's avatar
hareesh
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi @bteddy ,

first thing your module name and top level entity in your project both are different. you need to change that.

second thing in your code you have not declare so many of signals. because of that you are getting those warnings. those are marked in bellow attachment.

Thanks,