Forum Discussion

bteddy's avatar
bteddy
Icon for New Contributor rankNew Contributor
4 years ago

Getting errors when I run analysis and elaboration.

Hello, I have a verilog file "10ustep_stepperdriver.v" attached. Using Quartus II 64-bit ver.13.1 web edition. I was trying to run analysis and elaboration to get a RTL netlist (schematic). I...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

You're getting all those warnings because you are defining a whole bunch of signals without creating signal (wire) declarations.

The error is most likely because you've named the top-level entity in your Quartus project 10ustep, but the module name in this code is DRV_10uSTP. Change the code or change the name of the top-level entity for the project.