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Altera_Forum
Honored Contributor
Honored Contributorgetting crazy with FSM in VHDL. The FSM runs weird and misbehavior
background: To Let FPGA (cyclone 3) communication with a DSP board. i am trying to send three datas from DSP board to the FPGA board. code: library ieee;use ieee.std_logic_1164.all;
u...
Altera_ForumHonored Contributor
Honored ContributorOK. IF you don't have a scope, please set up SignalTap in your FPGA design and monitor the DSP_ACK signal. You need to know whether that signal triggers high, because then you will know which part of your design to debug. Right now there is not enough information.
