getting compilation error

Hi,

I have the similar problem. I am doing the tutorial "Using the SDRAM on Altera’s DE2-115 Board with VHDL Designs" which have SOPC builder to generate VHDL file.

In top level entity light, there is already SOPC generated nios system is defined and instantiated as:

ARCHITECTURE Structure OF lights IS

COMPONENT nios_system

PORT ( clk_0 : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

in_port_to_the_Switches : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

zs_addr_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

zs_ba_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

zs_cas_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_cke_from_the_sdram_0 : OUT STD_LOGIC;

zs_cs_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_dq_to_and_from_the_sdram_0 : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);

zs_dqm_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

zs_ras_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_we_n_from_the_sdram_0 : OUT STD_LOGIC);

END COMPONENT;

BEGIN

--¡¡ Instantiate the Nios II system entity generated by the SOPC Builder.

NiosII: nios_system

PORT MAP (

clk_0 => CLOCK_50,

reset_n => KEY(0),

out_port_from_the_LEDs => LEDG,

in_port_to_the_Switches => SW,

zs_addr_from_the_sdram_0 => DRAM_ADDR,

zs_ba_from_the_sdram_0 => DRAM_BA,

zs_cas_n_from_the_sdram_0 => DRAM_CAS_N,

zs_cke_from_the_sdram_0 => DRAM_CKE,

zs_cs_n_from_the_sdram_0 => DRAM_CS_N,

zs_dq_to_and_from_the_sdram_0 => DRAM_DQ,

zs_dqm_from_the_sdram_0 => DRAM_DQM,

zs_ras_n_from_the_sdram_0 => DRAM_RAS_N,

zs_we_n_from_the_sdram_0 => DRAM_WE_N );

DRAM_CLK <= CLOCK_50;

END Structure;

Then why again separate file is generated without entity and component as:

--Example instantiation for system 'nios_system'

nios_system_inst : nios_system

port map(

out_port_from_the_LEDs => out_port_from_the_LEDs,

zs_addr_from_the_sdram_0 => zs_addr_from_the_sdram_0,

zs_ba_from_the_sdram_0 => zs_ba_from_the_sdram_0,

zs_cas_n_from_the_sdram_0 => zs_cas_n_from_the_sdram_0,

zs_cke_from_the_sdram_0 => zs_cke_from_the_sdram_0,

zs_cs_n_from_the_sdram_0 => zs_cs_n_from_the_sdram_0,

zs_dq_to_and_from_the_sdram_0 => zs_dq_to_and_from_the_sdram_0,

zs_dqm_from_the_sdram_0 => zs_dqm_from_the_sdram_0,

zs_ras_n_from_the_sdram_0 => zs_ras_n_from_the_sdram_0,

zs_we_n_from_the_sdram_0 => zs_we_n_from_the_sdram_0,

clk_0 => clk_0,

in_port_to_the_Switches => in_port_to_the_Switches,

reset_n => reset_n

);

and upon compilation giving following error:

Error (10500): VHDL syntax error at nios_system_inst.vhd(2) near text "nios_system_inst"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

When I remove this additional file, the compilation is successful but I am afraid of loading on FPGA concerning it may damage with incomplete/wrong program.

Any suggestion?

Thanks in advance