Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
What's your fpga clock frequency?
a-For example, if your fclk is 50MHz, count from 0 to 50MHz/40KHz=1250. b-add a comparator to the counter: when count<625 output is '1' else '0'. c-register the output to avoid glitches. - Altera_Forum
Honored Contributor
I is actually 50 MHz, yet I have a given clock divider so I have different possible outputs, such as: 1 MHz, 100KHz, 10KHz, 1KHz, 100Hz,and 1 Hz. Ok, Thanks