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Altera_Forum's avatar
Altera_Forum
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8 years ago

Generated clock

Hello, i will create a generated clock and need your help. I have a counter (1 to 2500), which increments every rising edge of clk. Then i set enable to "1" for one clock cycle and set it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

there is no clock input in U4. It stores the ADC samples (sampling frequency 1MHz). Whenever i have a rising edge of enable (generated by U6), the outputs of U3 and U4 should be updated.

So, when i use the enable as clock i need a generated clock constraint, right? Now, my enable signal is "0" till 2049 and "1" by 2500. How can i define it in my SDC file? Is it a proper way?

To your suggestion with adding a clock:

Just adding a clock to U4 and update the output whenever enable is set to "1"?