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Altera_Forum's avatar
Altera_Forum
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7 years ago

Generated clock

Hello, i will create a generated clock and need your help. I have a counter (1 to 2500), which increments every rising edge of clk. Then i set enable to "1" for one clock cycle and set it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

This is an SDC question, not VHDL.

Are you saying that this "enable" signal you are creating drives clock inputs elsewhere in the design? If not, you don't even need this constraint. Or are you saying that enable is being fed out of the FPGA device?

50MHz/5000=10KHz. That doesn't match the description of your design. Why not divide by 2500?