Generate PWM signal

The comparator looks better. The threshold for comparator would be 410 (512 *80%) for 80% high pulse.

I just did some modelling and found out that another equivalent way is to restrain the accumulator maximum.

For example for 20% high,80%low:

stop accumulator at 320 maximum instead of free 511.

then low occurs at a ratio of 256/320 = 80%

Thus a comparator fixed at 256 is implied but accumulator max is changed.

You can visualise this accum result as a full cycle wheel that is 0 at one half (0:255) then 1 at next half(256:511) and then you control size of each half of the wheel.

The input PWM_in will be a constant that determines frequency of pulse with low value meaning low frequency. The pulse will not be exactly regular but tends towards target duty cycle on average.

the modified version:

1. module PWM(clk, PWM_in, PWM_out);

2. input clk;

3. input [7:0] PWM_in;

4. output PWM_out;

5. reg [8:0] PWM_accumulator;

6. always @(posedge clk)

if (PWM_accumulator + PWM_in) > 319

PWM_accumulator <= 0;

else

PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;

7. assign PWM_out = PWM_accumulator[8];

8. endmodule

But overall FvM algorithm is better for resource.