Generate PWM signal

As a first point, I have to correct my previous statement. For 50% duty cycle, the code has to be changed to

PWM_accumulator <= PWM_accumulator + FREQ_in

Originally, the output is one clock cycle high and X cyles low. But it's neither a PWM.

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I think it can if PWM_in is varied in time.

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It can. But if you ask me for a PWM code, I'll suggest a basic PWM generator.

A typical PWM generator is comprised of a ramp generator and a comparator. I keep the variable frequency feature of the previous code to show an option.

module PWM(clk, PWM_in, PWM_out);
input clk;
input  FREQ_in;
input  PWM_in;
output PWM_out;
reg  PWM_accumulator;
always @(posedge clk) 
begin
PWM_accumulator <= PWM_accumulator + FREQ_in;
PWM_out = (PWM_IN > PWM_accumulator);
end
endmodule