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In general, you Cannot make the FPGA generate a clock. You must provide a clock into the FPGa from something like an Oscillator, or from some other chip that can generate a clock source like a Dallas Semiconductor (now Maxim) clock source device.
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Avatar,
This is exactly what I was going to point out to myself in a response to a question I was about to post. However, I must still ask:
Why is there# xx delay statement in Verilog or to put it another way - why are there so many examples of how we can "generate" a clock with:
@always# 10 q= ~q
That never made sense to me? How would the FPGA know what the length of 10 time units is and where do the time units come from in the first place? Is this some evil compiler thing or does it exist PURELY SYNTHENICALLY only within the software environment for the purpose of testing and simulation?
And even if this is synthetic concept, how does one tell the compiler what one time unit is and where is the counting kept for this to work? Is it all transparent to the Quartus2 user?
In my mind I see serious conceptual problems when I encounter “assign# xx” statements. I would appreciate another blunt to-the-money paragraph on this if you have the time.
Thanks much
~B
Honored Contributor
