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Altera_Forum
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18 years ago

generate clock with Quartus 7.1 web adition

Hello everyone, I've asked here before how can I make the FPGA generate a clock with Quartus 7.1. I read the user guide you told me and I used the MegaWizard Plug-In Manager (ALTPLL) in or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi Marc, this is weird. Do you specify the library altera_mf using the "-L" switch when you simulate your source code? For example to run RTL simulation:

vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L rtl_work -L work an_dcfifo_top_vlg_vec_tst

If not sure, you can try run the native-link (Tools->EDA Simulation Tool->RUN EDA RTL Simulation) see whether you get the same error. Hope it helps.