Honored Contributor
Honored ContributorHi Pookipsit, in case you haven't got your answer yet, when you run your megawizard, you can specify the output file name. That is the module name that will be created (e.g. mypll). You can instantiate the "mypll" - output file name that you name in another verilog code. For example:
mypll PLL0( .inclk0(clk), .c0(pll_out)); Download the design example at http://www.altera.com/support/examples/modelsim/exm-siigx-timing-vhdl-msaltera.html You can see how the top-level alt2gxb_example.v instantiate the mypll in mypll.v (generated by Megawizard). Hope it helps.
