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Altera_Forum's avatar
Altera_Forum
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18 years ago

generate clock with Quartus 7.1 web adition

Hello everyone, I've asked here before how can I make the FPGA generate a clock with Quartus 7.1. I read the user guide you told me and I used the MegaWizard Plug-In Manager (ALTPLL) in or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

In the same kind of subject, I generated a PLL with the ALTPLL function, but even when the compilation is okay after inserting an instance in my design, it's impossible to simulate nor synthetise it in Quartus... Is therer a basic standard process in order to do that properly ? The Cyclone II Handbook isn't very complete in how to do that.

Thank you very much!