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Altera_Forum's avatar
Altera_Forum
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18 years ago

generate clock with Quartus 7.1 web adition

Hello everyone, I've asked here before how can I make the FPGA generate a clock with Quartus 7.1. I read the user guide you told me and I used the MegaWizard Plug-In Manager (ALTPLL) in or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You can use "map" in vhdl. A handbook is good for you.

You can also do as follows.After compiling your project(written with vhdl or verilog),"File\Create/update\Create sambol files for current file", then you can insert it in your other projects.

Hope it can help you!

Regards.