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Altera_Forum's avatar
Altera_Forum
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18 years ago

generate clock with Quartus 7.1 web adition

Hello everyone, I've asked here before how can I make the FPGA generate a clock with Quartus 7.1. I read the user guide you told me and I used the MegaWizard Plug-In Manager (ALTPLL) in or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

If you are using HDL flow, you should use the instance that is generated by megawizard. Refer to the generated verilog or vhdl file for this. Wire the input/output in your design file for the generated pll just like you connect any other modules in HDL design flow and you can use this pll in your design.

If you are using schematic flow, you should use the generated bsf file of the pll. You may have to generate the bsf for your design file. If you are using SOPC builder flow, the bsf for your system must have been automatically generated by SOPC builder.