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Altera_Forum's avatar
Altera_Forum
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7 years ago

Generate an IP core using Quartus Standard Edition 30-days evaluation period

Hi, I have experience with other FPGA manufacturer and respective tools an now I have to send my VHDL code to other entity/person that will run in an INTEL FPGA (Stratix IV). That entity/pers...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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I think features like partial configuration and netlist generation are only available with a full licence.

Any reason you cannot just provide the source code to the 3rd party?

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IP protection, this is why I want to generate an IP of my VHDL code.