General timing constraints workflow?

Thanks Jake. I have taken a look at timequest but it seemed to me that i don't need the fancy stuff at this time since i "just wanted to constrain the timings in the current design".

Essentially, i'm trying to figure out why my design fails one out of every five times it runs on the same board. I doubt it has anything to do with I/O timings since all timings look ok when actually measured on my board but i want to rule this out by doing basic constraining of the I/O.

I'm using a Cyclone II and the timing margins are large so the classic timing analyzer should work well enough for this project.

Thanks,

/John.