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Altera_Forum's avatar
Altera_Forum
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16 years ago

gated clock

I have a 100 Mhz clock coming to my FPGA CLOCK100. This goes to the SOPC which has a PLL. The PLL generates a 150 MHz clock CLOCK150 which goes to my custom logic which has a PLL. The output of the P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The top level is a schematic.

My custom block is in verilog.

One more related question.In my SDC file I define the clock to the input port only (which is input clock to PLL in SOPC). Then I use

derive_pll_clocks to derive other clock.

Do I need to define clock to the 2nd PLL (in my custom logicic) which gets its input from the output of the 1st PLL.

I am getting some timing violations (from the output of the SOPC registers which run off the 1st PLL) to the input registers in custom logic running off 2nd PLL.