Gate Level Synthesis: Signals

I agree with the commentary so far that gate-level sims are pretty painful and often not necessary. Did you do your functional simulation in Quartus II or did you simulate the HDL in Modelsim or some other third-party simulator? If you simulated with Quartus II, then there are two possibilities. 1) There's an actual synthesis bug in the software 2) Your design needs more timing constraints. Quartus II actually functionally simulates the initial netlist coming from elaboration but prior to any fancy optimizations and technology mapping. So it must be at least partially correct.

If you're starting with third-party functional sim of the HDL, then both possibilities apply again. I'd usually start by functionally simulating the design in Quartus II. If it passed, I'd look for timing problems first, then start pointing fingers at the software. Did you enable any crazy optimizations? As with software compiler optimizations, the scarier the hardware optimization, the more likely it's not 100% correct. I'd do a very vanilla compile on a couple different families and speed grades.

You can always add preserve attributes to important registered signals and keep attributes to important non-registered signals. These attributes should preserve those points in your design.

Well, good luck!