Gate Level Synthesis: Signals

For me signal tap usage became less important with recent designs, since a) the speeds are too high to be able to sample, b) the number of clock domains increase thus errors appear elsewhere than expexted, and signal tap sampled c) Signal Tap usage modified the design strongly or made it even impossible to fit.

I more and more prefere a design technique, where test features are included in the full design, e.g. temporary results are stored into additional RAMs (therefore, using prototyping boards with larger divices is a good recommendation) or or forged to pipe lined output. These "trace logic" parts become a fixed part of the design and could later be used to trace errors of the complete system too, e.g. supporting the process optimization at the customer's plant ...

Refering to RTL Simulation : Since most of the deisgn somehow are check in a complete environment (when possible) a more or less complete test bench with models is present anyway. So there is not much worl to do to compile the *vho an invoke an over night simulation of some micro seconds of the design.

If necessary, I keep design parts switchable and bridgeable to shun large algorithmic sections in a design, which could cause the simulator to become too slow. So I am simulation the full design but can concentrate on clock boundaries, IO-sampling issues and such.

And yes, I allready found some misbehaviour in design, caused by wrong contraints or misunderstandings of delays in data sheets.