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Altera_Forum's avatar
Altera_Forum
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8 years ago

gate level simulation with time constranit

hi. I thought about this problem about days and days... I really need your help. I want to design so that maximum operating frequency is 100MHz. So I added D register in middle of my RTL code t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Solatidore,

What device that you were using? If you were using V series, gate level simulation is not supported.

Best Regards,

kentan

(This message was posted on behalf of Intel Corporation)